Static random access memory or SRAM devices comprising a plurality of memory cells are typically configured as an array of rows and columns, with one or more I/Os (e.g., ×4, ×8, ×16, etc. configurations). Also, such memories may be provided in a multi-bank architecture for applications where high density, high speed and low power are required. Regardless of the architecture and type, each SRAM cell is operable to store a single bit of information. Access to this information is facilitated by activating all memory cells in a given physical row (by driving a wordline associated therewith) and outputting the data onto bitlines associated with a selected column for providing the stored data value to the selected output. Once the data is disposed on the bitlines, voltage levels on the bitlines begin to separate to opposite power supply rails (e.g., VDD and ground), and a sense amplifier is utilized to latch the logic levels sensed on the bitlines after they are separated by a predetermined voltage difference, typically ten percent or less of VDD. Furthermore, the sense amplifier may be provided as a differential sense amplifier, with each of the memory cells driving both a data signal and a data-bar signal on the complementary bitlines (e.g., data lines) associated with each column. In operation, prior to activating the memory cells, the bitlines are precharged and equalized to a common value. Once a particular row and column are selected, the memory cell corresponding thereto is activated such that it pulls one of the data lines toward ground, with the other data line remaining at the precharged level, typically VDD. The sense amplifier coupled to the two complementary bitlines senses the difference between the two bitlines once it exceeds a predetermined value and the sensed difference is indicated to the sense amplifier as the differing logic states of “0” and “1”.
As the transistor device sizes continue to decrease, e.g., 0.13 microns or smaller, several issues begin to emerge with respect to the operation of SRAM cells, chiefly because at such dimensions the devices suffer from high values of leakage in the off state in standby mode. Essentially, these devices are no longer ideal switches; rather they are closer to sieves, having a non-negligible constant current flow path from drain to source or from drain/source to substrate even in the off state. The high leakage causes two major problems. First, because of the generation of large static current as leakage, there is increased static power consumption as a result. Second, which is more serious, is the issue of incorrect data reads from the SRAM cells. The accumulated leakage current from all the bitcells in a selected column is now comparable to the read current, thereby significantly eroding the bitline differential required for reliable sensing operations.
A technique for reducing standby leakage currents in a SRAM cell is disclosed in “16.7 fA/cell Tunnel-Leakage-Suppressed 16 Mb SRAM for Handling Cosmic-Ray-Induced Multi-Errors” by Kenichi Osada, Yoshikazu Saitoh, Eishi Ibe and Koichiro Ishibashi (in IEEE International Solid-State Circuits Conference, 2003, pages 302 303), where the source terminals of a plurality of SRAM cells on a single bitline column are coupled together for providing a biasing potential. Whereas such a scheme is seen to reduce total standby current, it does not improve the ratio of read current (IR) to cell leakage current (IL), however.
A technique for reducing standby leakage currents in SRAM cells is also disclosed in U.S. Pat. No. 7,061,794 B1. As disclosed therein, when memory cells of a given sector are in standby mode, the write-lines to each physical row of memory cells in the sector are in a deselected state whereas the sector source lines are driven to a select potential in order to reduce memory leakage. When a memory read is activated for a given physical row in the sector, the write line associated with the desired physical row is driven high. This causes the logic associated with the desired physical row to drive the source line for the physical row low. The source lines for other physical rows in the sector are maintained at the selected (biased) potential. The voltage differentials of each of the cells in the selected physical row are sensed and the memory cells are restored to standby mode upon the commencement of another read operation for another physical row.
While the memory architectures disclosed in U.S. Pat. No. 7,061,794 B1 are very useful in their own right, they suffer some drawbacks. The disclosed memory architectures require logic for biasing each physical row in the SRAM. In particular, the decoding logic and the biasing circuit are part of the X-decoder (X-address decoder). This extra logic presents an overhead for each of the physical rows in the memory thereby causing significant overall area overhead. In other words, this extra logic takes up space on the chip that could otherwise be used for other functions, such as placement of additional memory cells. Moreover, the biasing logic in the memory architectures disclosed in U.S. Pat. No. 7,061,794 B1 are in the access path, resulting in significant speed loss. Additionally, the bias voltage used to bias cells in the memory architectures disclosed in U.S. Pat. No. 7,061,794 B1 cannot be adjusted. This represents another drawback because it has been determined that slight variances in the doping of silicon, and/or other features of silicon that affect the optimum value for preventing voltage leakage. In other words, different silicon environments dictate different bias voltages in order to minimize the amount of leakage.
Given the above-background, what are needed in the art are improved systems and methods for reducing leakage in SRAM.
Discussion or citation of a reference herein will not be construed as an admission that such reference is prior art.